{"id":86,"date":"2025-03-12T11:13:50","date_gmt":"2025-03-12T15:13:50","guid":{"rendered":"https:\/\/sites.nd.edu\/adingler\/?page_id=86"},"modified":"2025-03-17T10:03:56","modified_gmt":"2025-03-17T14:03:56","slug":"cse-20221-logic-design-and-sequential-circuits","status":"publish","type":"page","link":"https:\/\/sites.nd.edu\/adingler\/teaching\/cse-20221-logic-design-and-sequential-circuits\/","title":{"rendered":"CSE 20221 – Logic Design and Sequential Circuits"},"content":{"rendered":"\n

The information below is based on the Spring 2025<\/strong> section of CSE 20221.<\/p>\n\n\n\n

Overall Course Goals<\/strong><\/h3>\n\n\n\n

By the end of the course, you should:<\/p>\n\n\n\n

    \n
  1. Have a good basic understanding of the inner workings of a digital computer, including the main structures and abstractions used in a design, from basic Boolean operations made out of switches, up through a complete microprocessor executing an assembly language program.<\/li>\n\n\n\n
  2. Be able to independently <\/em>design and debug a moderately complex digital system, demonstrating proficiency of critical implementation techniques applicable to both hardware and software design, including the use of appropriate diagrams and tables to guide implementation and using a hypothesis-based approach to identify bugs.<\/li>\n<\/ol>\n\n\n\n

    Specific Learning Objectives<\/strong><\/h3>\n\n\n\n

    By the end of this course you should be able to:<\/p>\n\n\n\n

      \n
    1. Formulate logic expressions using the basic AND, OR, and NOT operations and implement these expressions as switching circuits.<\/li>\n\n\n\n
    2. Use the properties of Boolean algebra, as well as graphical tools to simplify logic expressions<\/li>\n\n\n\n
    3. Design fundamental combinational logic building blocks such as decoders, multiplexors, and adders using basic logic gates<\/li>\n\n\n\n
    4. Implement a latch and a register (flip-flop) using primitive logic gates, and to use registers to implement common sequential building blocks such as register files, counters, and timers<\/li>\n\n\n\n
    5. Develop a finite state machine (FSM) diagram that describes sequential behavior and then implement the FSM using registers and combinational logic<\/li>\n\n\n\n
    6. Design a high-level state machine (HLSM) that describes the algorithmic behavior of a digital system and then implement a digital system based on the HLSM with a datapath and FSM<\/li>\n\n\n\n
    7. Explain the organization of a simple multicycle microprocessor and write assembly language programs for that processor<\/li>\n\n\n\n
    8. Explain the need for, organization of, and data movement within a memory hierarchy including the register file, a first-level direct-mapped data cache, and a main memory.<\/li>\n\n\n\n
    9. Use a digital logic design tool and simulator to design and simulate simple combinational logic circuits, storage elements, hardware components for simple functional units, finite state machines, and simple processor datapaths.<\/li>\n<\/ol>\n\n\n\n

      Grading<\/strong><\/h3>\n\n\n\n
      Homework<\/td>35%<\/td>Weighted equally by score as percentage<\/td><\/tr>
      Readings<\/td>5%<\/td>zyBook readings will be due on most class days<\/td><\/tr>
      Midterm Exam 1<\/td>17.5%<\/td>Thursday 2\/20 in class, on paper<\/td><\/tr>
      Midterm Exam 2<\/td>17.5%<\/td>Thursday 4\/10 in class, on paper<\/td><\/tr>
      Final Exam<\/td>25%<\/td>Thursday 5\/8 7:30pm-9:30pm
      Same format as the two midterms but cumulative<\/strong><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

      Course Schedule<\/strong><\/h3>\n\n\n\n
      Date<\/td>Lecture<\/td>Readings<\/td>Homework<\/td><\/tr>
      Tu 01\/14\/25<\/td>L01: Course Introduction; Bits and Bytes<\/td>Reading 01: Introduction<\/td>HW01: Number Representation and C assigned<\/td><\/tr>
      Th 01\/16\/25<\/td>L02: Number Representation<\/td>Reading 02: Numbers and Letters<\/td><\/td><\/tr>
      Tu 01\/21\/25<\/td>L03: Intro to albaCore and Assembly Language<\/td>Reading 03: Intro to albaCore and Assembly Language (due Wed 11:59pm)<\/td>HW02: Introduction to albaCore and Assembly Language assigned
      (Tuesday)
      HW01 due (Wednesday)<\/td><\/tr>
      Th 01\/23\/25<\/td>L04: More albaCore and Assembly Language<\/td>Reading 04: albaCore Load, Store, Branches, and Jumps (due Thurs 9:30am)<\/td><\/td><\/tr>
      Tu 01\/28\/25<\/td>L05: albaCore Memory and Control Instructions<\/td>No reading due<\/td>HW03: More albaCore Programming assigned
      HW02 due<\/td><\/tr>
      Th 01\/30\/25<\/td>L06: albaCore Control \u2013 Selection, Loops and Procedures<\/td>Reading 05: Digital Circuits<\/td><\/td><\/tr>
      Tu 02\/04\/25<\/td>L07: albaCore Control Wrap-up and Digital Logic Intro<\/td>Reading 06: Boolean Algebra<\/td>HW04 Digital Circuits and Boolean Algebra assigned
      HW03 due<\/td><\/tr>
      Th 02\/06\/25<\/td>L08: Digital Logic, Boolean Algebra, Simplification<\/td>Reading 07: Logic Optimization<\/td><\/td><\/tr>
      Tu 02\/11\/25<\/td>L09: K-maps and Combinational Logic Components<\/td>Reading 08: Combinational Logic Components (Part 1)<\/td>HW05 Adder\/Subtractor assigned
      HW04 due Wed.<\/strong><\/td><\/tr>
      Th 02\/13\/25<\/td>L10: More Comb. Logic Components and Adders<\/td>Reading 09: Combinational Logic Components (Part 2)<\/td><\/td><\/tr>
      Tu 02\/18\/25<\/td>L11: Exam 1 Review
      (extra review examples recording)<\/td>      		No reading due<\/td>No HW assigned
      HW05 due Wed.<\/strong><\/td><\/tr>
      Th 02\/20\/25<\/td>Midterm Exam 1 (L12)<\/td>No reading due<\/td><\/td><\/tr>
      Tu 02\/25\/25<\/td>L13: Sequential Logic Introduction<\/td>Reading 10: ND Latches and FFs<\/td>HW06 Basic Calculator assigned<\/td><\/tr>
      Th 02\/27\/25<\/td>L14: Flip Flops and Registers<\/td>Reading 11: Latches, Flip Flops, and Registers<\/td><\/td><\/tr>
      Tu 03\/04\/25<\/td>L15: Register Examples<\/td>Reading 12: Load Registers, Counters, Timers<\/td>HW06 due<\/td><\/tr>
      Th 03\/06\/25<\/td>L16: Register Files and Memories<\/td>Reading 13: Register Files and Memory<\/td><\/td><\/tr>
      Tu 03\/11\/25<\/td>Spring Break<\/td><\/td><\/td><\/tr>
      Th 03\/13\/25<\/td>Spring Break<\/td><\/td><\/td><\/tr>
      Tu 03\/18\/25<\/td>L17: Finite State Machines<\/td>Reading 14: Finite State Machines<\/td>HW07 Programmable Calculator assigned<\/td><\/tr>
      Th 03\/20\/25<\/td>L18: Finite State Machine Design<\/td>Reading 15: FSM Design and Analysis<\/td><\/td><\/tr>
      Tu 03\/25\/25<\/td>L19: FSM Examples and HLSM Intro<\/td>Reading 16: HLSMs Part 1<\/td>HW07 due
      HW08 Finite State Machines assigned<\/td><\/tr>
      Th 03\/27\/25<\/td>L20: High-level State Machines<\/td>Reading 17: HLSMs Part 2<\/td><\/td><\/tr>
      Tu 04\/01\/25<\/td>L21: HLSM Examples<\/td>No reading due<\/td>HW08 due
      HW09 Design of a Hardware Multiplier assigned<\/td><\/tr>
      Th 04\/03\/25<\/td>L22: Back to albaCore<\/td>Reading 18: albaCore HLSM, etc.<\/td><\/td><\/tr>
      Tu 04\/08\/25<\/td>L23: Midterm Exam 2 Review<\/td>No reading due<\/td>HW09 due<\/td><\/tr>
      Th 04\/10\/25<\/td>Midterm Exam 2 (L24)<\/td>No reading due<\/td><\/td><\/tr>
      Tu 04\/15\/25<\/td>L25: albaCore Wrap-up<\/td>No reading due<\/td>HW10 Caches assigned<\/td><\/tr>
      Th 04\/17\/25<\/td>L26: Cache Introduction<\/td>Reading 19: Caches (Part 1)<\/td><\/td><\/tr>
      Tu 04\/22\/25<\/td>L27: Direct-mapped Caches<\/td>Reading 20: Caches (Part 2) (last reading)<\/td><\/td><\/tr>
      Th 04\/24\/25<\/td>L28: Direct-Mapped Cache Wrap-up<\/td>No reading due<\/td><\/td><\/tr>
      Tu 04\/29\/25<\/td>L29: Wrap-up and Final Exam Review<\/td><\/td>HW10 due<\/td><\/tr><\/tbody><\/table><\/figure>\n","protected":false},"excerpt":{"rendered":"

      The information below is based on the Spring 2025 section of CSE 20221. Overall Course Goals By the end of the course, you should: Specific Learning Objectives By the end of this course you should be able to: Grading Homework 35% Weighted equally by score as percentage Readings 5% zyBook readings will be due on […]<\/p>\n","protected":false},"author":4492,"featured_media":0,"parent":16,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"class_list":["post-86","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/pages\/86","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/users\/4492"}],"replies":[{"embeddable":true,"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/comments?post=86"}],"version-history":[{"count":6,"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/pages\/86\/revisions"}],"predecessor-version":[{"id":98,"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/pages\/86\/revisions\/98"}],"up":[{"embeddable":true,"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/pages\/16"}],"wp:attachment":[{"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/media?parent=86"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}