{"id":93,"date":"2025-03-17T09:59:38","date_gmt":"2025-03-17T13:59:38","guid":{"rendered":"https:\/\/sites.nd.edu\/adingler\/?page_id=93"},"modified":"2025-03-17T10:01:08","modified_gmt":"2025-03-17T14:01:08","slug":"cse-30321-computer-architecture","status":"publish","type":"page","link":"https:\/\/sites.nd.edu\/adingler\/teaching\/cse-30321-computer-architecture\/","title":{"rendered":"CSE 30321 – Computer Architecture"},"content":{"rendered":"\n

The information below is based on the Spring 2025<\/strong> section of CSE 30321.<\/p>\n\n\n\n

Course Goals<\/strong><\/h3>\n\n\n\n

By the end of this course you should be able to:<\/p>\n\n\n\n

    \n
  1. Describe the fundamental components required in a single core of a modern microprocessor as well as how they interact with each other, with main memory, and with external storage media.<\/li>\n\n\n\n
  2. Suggest, compare, and contrast potential architectural enhancements by applying appropriate performance metrics.<\/li>\n\n\n\n
  3. Apply fundamental knowledge about a processor\u2019s datapath, different memory hierarchies, performance metrics, etc. to design a microprocessor such that it (a) meets a target set of performance goals and (b) is realistically implementable.<\/li>\n\n\n\n
  4. Explain how code written in (different) high-level languages (like C, Java, C++, etc.) can be executed on different microprocessors (e.g., RISC-V, Intel, ARM, etc.) to produce the result intended by the programmer.<\/li>\n\n\n\n
  5. Use knowledge about a microprocessor\u2019s underlying hardware (or \u201carchitecture\u201d) to write more efficient software.<\/li>\n\n\n\n
  6. Describe the main architectural approaches to improve computer performance (circa 2004 and 2012).<\/li>\n\n\n\n
  7. Explain and articulate why modern microprocessors now have more than one core and how software must adapt to accommodate the now prevalent multi-core approach to computing.<\/li>\n<\/ol>\n\n\n\n

    Grading<\/strong><\/h3>\n\n\n\n
    Homework<\/td>35%<\/td>Weighted equally by score as percentage<\/td><\/tr>
    Readings<\/td>5%<\/td>zyBooks readings will be released on most class days.<\/td><\/tr>
    Midterm Exam 1<\/td>17.5%<\/td>Tuesday 2\/18<\/td><\/tr>
    Midterm Exam 2<\/td>17.5%<\/td>Tuesday 4\/8<\/td><\/tr>
    Final Exam<\/td>25%<\/td>Wednesday 5\/7 7:30-9:30pmSame format as the two midterms, but cumulative<\/strong><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

    Course Schedule<\/h3>\n\n\n\n
    Date<\/td>Lecture<\/td>Readings<\/td>Homework<\/td><\/tr>
    Tu 01\/14\/25<\/td>L01: Course Introduction; ISA and Processor Review<\/td>Reading 01: Introduction<\/td>HW01: ISA Review and RISC-V Intro assigned<\/td><\/tr>
    Th 01\/16\/25<\/td>L02: ISA Review and Performance Intro<\/td>None; review albaCore as needed or work ahead on next reading<\/td><\/td><\/tr>
    Tu 01\/21\/25<\/td>L03: Performance<\/td>Reading 02: Performance (open until Wed.)<\/td><\/td><\/tr>
    Th 01\/23\/25<\/td>L04: RISC-V Instructions and Programming<\/td>Reading 03: RISC-V Instruction Introduction<\/td>HW01 due
    HW02: Performance and Assembly Programming assigned<\/td><\/tr>
    Tu 01\/28\/25<\/td>L05: RISC-V Instruction Types and Encodings<\/td>Reading 04: RISC-V Instructions (R-, I-, S-, SB-types)<\/td><\/td><\/tr>
    Th 01\/30\/25<\/td>L06: RISC-V Control and Procedures<\/td>Reading 05: RISC-V Procedures (UJ-type, call\/return, stack)<\/td>HW03: RISC-V ISA and Function Calls
    assigned
    HW02 due<\/td><\/tr>
    Tu 02\/04\/25<\/td>L07: Recursive Function and Pipelining Introduction<\/td>Reading 06: Pipelining Intro<\/td><\/td><\/tr>
    Th 02\/06\/25<\/td>L08: Pipelining<\/td>Reading 07: Pipelining Details<\/td>HW04 Procedures, Pipelining, and Sorting assigned
    HW03 due<\/td><\/tr>
    Tu 02\/11\/25<\/td>L09: Pipelining Hazards<\/td>Reading 08: Pipelining Hazards<\/td><\/td><\/tr>
    Th 02\/13\/25<\/td>L10: Exam 1 Review<\/td>No reading due<\/td>HW04 due<\/td><\/tr>
    Tu 02\/18\/25<\/td>Midterm Exam 1 (L11)<\/td>No reading due<\/td><\/td><\/tr>
    Th 02\/20\/25<\/td>L12: Control Hazards<\/td>Review Control Hazards from Reading 08<\/td>HW05 Pipeline Control Hazards assigned
    No HW due<\/td><\/tr>
    Tu 02\/25\/25<\/td>L13: Control Hazard Examples, Memory Hierarchy Review<\/td>Reading 09: Memory Hierarchy Intro\/Review of Direct-mapped Caches<\/td><\/td><\/tr>
    Th 02\/27\/25<\/td>L14: Direct-mapped Caches<\/td>Reading 10: AMAT and Set Associative Caches<\/td>HW06 Caches assigned
    HW05 due<\/td><\/tr>
    Tu 03\/04\/25<\/td>L15: Associative Caches and Cache Examples<\/td>No reading due<\/td><\/td><\/tr>
    Th 03\/06\/25<\/td>L16: Cache Performance (no video)<\/td>Reading 11: Improving Cache Performance<\/td>HW06 due Friday<\/strong><\/td><\/tr>
    Tu 03\/11\/25<\/td>Spring Break<\/td><\/td><\/td><\/tr>
    Th 03\/13\/25<\/td>Spring Break<\/td><\/td><\/td><\/tr>
    Tu 03\/18\/25<\/td>L17: Cache-Aware Programming and Virtual Memory Intro<\/td>No reading due<\/td><\/td><\/tr>
    Th 03\/20\/25<\/td>L18: Virtual Memory (Paging)<\/td>Reading 13: Virtual Memory<\/td>HW07 Cache Performance assigned<\/td><\/tr>
    Tu 03\/25\/25<\/td>L19: VM Examples and Performance<\/td>Reading 14: VM Performance and the TLB<\/td><\/td><\/tr>
    Th 03\/27\/25<\/td>L20: VM Wrap-up<\/td>No reading due<\/td>HW07 due
    HW08 Virtual Memory assigned<\/td><\/tr>
    Tu 04\/01\/25<\/td>L21: Out-of-order Introduction<\/td>Reading 15: Multiple Issue, Static Scheduling<\/td><\/td><\/tr>
    Th 04\/03\/25<\/td>L22: Midterm Exam 2 Review<\/td>No reading due<\/td>HW08 due
    <\/td><\/tr>
    Tu 04\/08\/25<\/td>Midterm Exam 2 (L23)<\/td>No reading due<\/td><\/td><\/tr>
    Th 04\/10\/25<\/td>L24: Dynamic Scheduling<\/td>Reading 16: Dynamic Scheduling<\/td>HW09 Out of Order Execution assigned
    <\/td><\/tr>
    Tu 04\/15\/25<\/td>L25: Dynamic Scheduling Examples<\/td>No reading due<\/td><\/td><\/tr>
    Th 04\/17\/25<\/td>L26: Multi-core Introduction<\/td>Reading 17: Cache Coherence (last reading)<\/td>HW09 due
    HW10 Cache Coherence assigned<\/td><\/tr>
    Tu 04\/22\/25<\/td>L27: Cache Coherence<\/td>No reading due<\/td><\/td><\/tr>
    Th 04\/24\/25<\/td>L28: Cache Coherence Examples<\/td>No reading due<\/td>HW10 due<\/td><\/tr>
    Tu 04\/29\/25<\/td>L29: Wrap-up and Final Exam Review<\/td>No reading due<\/td><\/td><\/tr><\/tbody><\/table><\/figure>\n","protected":false},"excerpt":{"rendered":"

    The information below is based on the Spring 2025 section of CSE 30321. Course Goals By the end of this course you should be able to: Grading Homework 35% Weighted equally by score as percentage Readings 5% zyBooks readings will be released on most class days. Midterm Exam 1 17.5% Tuesday 2\/18 Midterm Exam 2 […]<\/p>\n","protected":false},"author":4492,"featured_media":0,"parent":16,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"class_list":["post-93","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/pages\/93","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/users\/4492"}],"replies":[{"embeddable":true,"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/comments?post=93"}],"version-history":[{"count":1,"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/pages\/93\/revisions"}],"predecessor-version":[{"id":96,"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/pages\/93\/revisions\/96"}],"up":[{"embeddable":true,"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/pages\/16"}],"wp:attachment":[{"href":"https:\/\/sites.nd.edu\/adingler\/wp-json\/wp\/v2\/media?parent=93"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}