As the CMOS transistor feature size is approaching its physical limit, we are witnessing an explosion of research endeavors in beyond-CMOS technologies. My work explores circuit and architecture designs that can best exploit the unique features of beyond-CMOS devices to maximize the gain offered by such devices. My research benefits greatly from close collaborations with device experts. Below are the several representation topics.<\/p>\n\n\n\n
Processing in memory (PIM)<\/strong> is an attractive architectural paradigm for overcoming the ever-growing challenge of transferring data between a processing element and memory in applications such as machine learning and data analytics applications. Beyond-CMOS devices, such as ferroelectric FETs (FeFETs), can function both as a switch and a storage element, hence is a natural fit for implementing PIM constructs. My group have introduced various FeFET based content addressable memories (e.g., ternary<\/a>, approximate<\/a>, multi-bit<\/a>), general-purpose compute-in-memory<\/a> arrays, binary crossbars arrays<\/a>, etc.<\/p>\n\n\n\n A paper<\/a> introducing an FeFET based compute-in-memory array, co-authored by my Ph.D. student, Dayane Reis, my colleague Mike Niemier and I, received the Best Paper Award<\/strong> from 2018 International Symposium on Low Power Electronics and Design. Another paper<\/a> from my group received the Best Paper Award<\/strong> from 2009 International Symposium on NanoScale Architectures. Below are other representative papers.<\/p>\n\n\n\n Secure hardware and hardware for security<\/strong>. Some unique characteristics, such as ambipolarity, of beyond-CMOS devices make these devices especially suited for building low-cost, secure hardware circuits. My group have introduced several novel circuits to achieve logic obfuscation and\/or prevent side channel attacks. We also proposed accelerators for homomorphic encryption. Below are some representative papers.<\/p>\n\n\n\n For more detailed description about my research projects in this area, please visit my lab at: TBD.<\/strong><\/p>\n\n\n\n My earlier research in the general circuit and architecture design is related to VLSI design and design automation. I have studied problems in high-level synthesis, VLSI floorplanning, and design of special VLSI circuitry for computationally intensive systems.<\/p>\n","protected":false},"excerpt":{"rendered":" As the CMOS transistor feature size is approaching its physical limit, we are witnessing an explosion of research endeavors in beyond-CMOS technologies. My work explores circuit and architecture designs that can best exploit the unique features of beyond-CMOS devices to maximize the gain offered by such devices. My research benefits greatly from close collaborations with […]<\/p>\n","protected":false},"author":3879,"featured_media":0,"parent":7,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-9","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/sites.nd.edu\/xsharon-hu\/wp-json\/wp\/v2\/pages\/9","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/sites.nd.edu\/xsharon-hu\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/sites.nd.edu\/xsharon-hu\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/sites.nd.edu\/xsharon-hu\/wp-json\/wp\/v2\/users\/3879"}],"replies":[{"embeddable":true,"href":"https:\/\/sites.nd.edu\/xsharon-hu\/wp-json\/wp\/v2\/comments?post=9"}],"version-history":[{"count":3,"href":"https:\/\/sites.nd.edu\/xsharon-hu\/wp-json\/wp\/v2\/pages\/9\/revisions"}],"predecessor-version":[{"id":60,"href":"https:\/\/sites.nd.edu\/xsharon-hu\/wp-json\/wp\/v2\/pages\/9\/revisions\/60"}],"up":[{"embeddable":true,"href":"https:\/\/sites.nd.edu\/xsharon-hu\/wp-json\/wp\/v2\/pages\/7"}],"wp:attachment":[{"href":"https:\/\/sites.nd.edu\/xsharon-hu\/wp-json\/wp\/v2\/media?parent=9"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}