{"id":2,"date":"2020-02-10T20:25:40","date_gmt":"2020-02-10T20:25:40","guid":{"rendered":"http:\/\/sites.nd.edu\/zheyu-yan\/?page_id=2"},"modified":"2025-01-09T05:17:26","modified_gmt":"2025-01-09T09:17:26","slug":"sample-page","status":"publish","type":"page","link":"https:\/\/sites.nd.edu\/zheyu-yan\/","title":{"rendered":"Zheyu Yan"},"content":{"rendered":"<p><strong>Email<\/strong>:\u00a0 zyan2 at nd.edu<br \/>\n<strong>Office<\/strong>: 254 Fitzpatrick<\/p>\n<h2>Introduction<\/h2>\n<p><strong>Zheyu is now an Assistant Professor at Zhejiang University.<\/strong><\/p>\n<p>Zheyu received his Ph.D.\u00a0 from the Department of Computer Science and Engineering at the University of Notre Dame in 2024.\u00a0 He received B.S. from Zhejiang University, Hangzhou, China, and joined the Notre Dame family in 2019. He is co-advised by <a href=\"https:\/\/www3.nd.edu\/~scl\/index.html\">Dr. Yiyu Shi<\/a> and <a href=\"https:\/\/www3.nd.edu\/~shu\/\">Dr. X. Sharon Hu<\/a>.<\/p>\n<p>His general research direction is hardware\/software co-design for neuromorphic computing. His current interests are uncertainty modeling of non-volatile emerging device-based neural accelerators and achieving efficient DNN inference via co-design efforts.<\/p>\n<p><strong>He is currently on the market!<\/strong><\/p>\n<p>His CV can be found <a href=\"https:\/\/github.com\/MariusAnje\/MariusAnje.github.io\/blob\/6542153bb755fc8809f76731df1ac49ba8e344f0\/Zheyu_Yan_Resume_2023.pdf.pdf\">here<\/a>.<\/p>\n<h2>Education<\/h2>\n<p>Ph.D. Student, Computer Science and Engineering, <strong>University of Notre Dame<\/strong>, IN, 2019 &#8211; present<br \/>\nB.S., Electronic Science and Technology, <strong>Zhejiang University<\/strong>, Hangzhou, 2019<\/p>\n<h2>Skills and Awards<\/h2>\n<p><strong>Coding: \u00a0 <\/strong>Verilog, Assembly, C, Python<br \/>\n<strong>Toolkits:\u00a0 <\/strong>PyTorch, Vivado, Altium Designer<br \/>\n<strong>Awards:<\/strong><\/p>\n<ul>\n<li>William J. McCalla ICCAD <strong>Best Paper Award<\/strong><\/li>\n<li>First place, the 31st ACM SIGDA University Demonstration at DAC 2021<\/li>\n<li>Design Automation Conference (DAC) Young Fellows 2021<\/li>\n<li>China National Scholarship (top 0.2%)<\/li>\n<\/ul>\n<h2>Leadership and Services<\/h2>\n<p><strong>Academic Director\/Organizer<\/strong>, Model United Nations Association of Zhejiang University, 2015-2018<br \/>\n<strong>Teaching Assistant<\/strong>, Theory of Computing, Fall 2019<br \/>\n<strong>Teaching Assistant<\/strong>, Elements of Computing II, Spring 2019<\/p>\n<h2>Selected Publications<\/h2>\n<h3>Journals<\/h3>\n<ol>\n<li><strong>Zheyu Yan<\/strong>, Xiaobo Sharon Hu, and Yiyu Shi. &#8220;U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators.&#8221; <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems<\/i>\u00a0(2024).<\/li>\n<li><strong>Zheyu Yan<\/strong>, Xiaobo Sharon Hu, and Yiyu Shi. &#8220;Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections.&#8221; <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems<\/i>\u00a0(2024).<\/li>\n<li>Weiwen Jiang, Qiuwen Lou, <strong>Zheyu Yan<\/strong>, Lei Yang, Jingtong Hu, X. Sharon Hu and Yiyu Shi, &#8220;Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators,&#8221; IEEE Transactions on Computers<\/li>\n<\/ol>\n<h3>Conferences<\/h3>\n<ol>\n<li><strong>Zheyu Yan<\/strong>, Yifan Qin, X. Sharon Hu and Yiyu Shi, &#8220;Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noise,&#8221; in Proc. of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 2023<\/li>\n<li><strong>Zheyu Yan<\/strong>, X. Sharon Hu and Yiyu Shi, &#8220;Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?,&#8221; in Proc. of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 2022<\/li>\n<li><strong>Zheyu Yan<\/strong>, X. Sharon Hu and Yiyu Shi, &#8220;SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerator,&#8221; in Proc. of IEEE\/ACM Design Automation Conference (DAC), 2022<\/li>\n<li><strong>Zheyu Yan<\/strong>, Weiwen Jiang, Xiaobo Sharon Hu, Yiyu Shi, &#8220;RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search,&#8221; in Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2022<\/li>\n<li><strong>Zheyu Yan<\/strong>, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo, &#8220;When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies&#8221; in Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2020<\/li>\n<li>\u00a0<strong>Zheyu Yan<\/strong>, Da-Cheng Juan, X. Sharon Hu and Yiyu Shi, &#8220;Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search,&#8221; in Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2021 (Invited Paper)<\/li>\n<li>Xuan Wang, <strong>Zheyu Yan<\/strong>, et al. &#8220;DASALS: Differentiable Architecture Search-Driven Approximate Logic Synthesis.&#8221; <i>2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD)<\/i>. IEEE, 2023.<\/li>\n<li>Lei Yang, Weiwen Jiang, <strong>Zheyu Yan<\/strong>, Tushar Krishna, Hyouk Jun Kwon, Meng Li, Yiyu Shi, &#8220;Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks,&#8221; Design Automation Conference (DAC) 2020<\/li>\n<\/ol>\n<h3>Book Chapters<\/h3>\n<ol>\n<li><strong>Zheyu Yan<\/strong>, Xiaobo Sharon Hu, and Yiyu Shi. &#8220;On the Reliability of Computing-in-Memory Accelerators for Deep Neural Networks.&#8221; <i>System Dependability and Analytics: Approaching System Dependability from Data, System and Analytics Perspectives<\/i>. Cham: Springer International Publishing, 2022. 167-190.<\/li>\n<li><strong>Zheyu Yan<\/strong>, et al. &#8220;Hardware\u2013Software Co-design of Deep Neural Architectures: From FPGAs and ASICs to Computing-in-Memories.&#8221; <i>Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing: Software Optimizations and Hardware\/Software Codesign<\/i>. Cham: Springer Nature Switzerland, 2023. 271-301.<\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"<p>Email:\u00a0 zyan2 at nd.edu Office: 254 Fitzpatrick Introduction Zheyu is now an Assistant Professor at Zhejiang University. Zheyu received his Ph.D.\u00a0 from the Department of Computer Science and Engineering at the University of Notre Dame in 2024.\u00a0 He received B.S. from Zhejiang University, Hangzhou, China, and joined the Notre Dame family in 2019. He is [&hellip;]<\/p>\n","protected":false},"author":3696,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-2","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/sites.nd.edu\/zheyu-yan\/wp-json\/wp\/v2\/pages\/2","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/sites.nd.edu\/zheyu-yan\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/sites.nd.edu\/zheyu-yan\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/sites.nd.edu\/zheyu-yan\/wp-json\/wp\/v2\/users\/3696"}],"replies":[{"embeddable":true,"href":"https:\/\/sites.nd.edu\/zheyu-yan\/wp-json\/wp\/v2\/comments?post=2"}],"version-history":[{"count":32,"href":"https:\/\/sites.nd.edu\/zheyu-yan\/wp-json\/wp\/v2\/pages\/2\/revisions"}],"predecessor-version":[{"id":76,"href":"https:\/\/sites.nd.edu\/zheyu-yan\/wp-json\/wp\/v2\/pages\/2\/revisions\/76"}],"wp:attachment":[{"href":"https:\/\/sites.nd.edu\/zheyu-yan\/wp-json\/wp\/v2\/media?parent=2"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}