The information below is based on the Spring 2025 section of CSE 30321.
Course Goals
By the end of this course you should be able to:
- Describe the fundamental components required in a single core of a modern microprocessor as well as how they interact with each other, with main memory, and with external storage media.
- Suggest, compare, and contrast potential architectural enhancements by applying appropriate performance metrics.
- Apply fundamental knowledge about a processor’s datapath, different memory hierarchies, performance metrics, etc. to design a microprocessor such that it (a) meets a target set of performance goals and (b) is realistically implementable.
- Explain how code written in (different) high-level languages (like C, Java, C++, etc.) can be executed on different microprocessors (e.g., RISC-V, Intel, ARM, etc.) to produce the result intended by the programmer.
- Use knowledge about a microprocessor’s underlying hardware (or “architecture”) to write more efficient software.
- Describe the main architectural approaches to improve computer performance (circa 2004 and 2012).
- Explain and articulate why modern microprocessors now have more than one core and how software must adapt to accommodate the now prevalent multi-core approach to computing.
Grading
| Homework | 35% | Weighted equally by score as percentage |
| Readings | 5% | zyBooks readings will be released on most class days. |
| Midterm Exam 1 | 17.5% | Tuesday 2/18 |
| Midterm Exam 2 | 17.5% | Tuesday 4/8 |
| Final Exam | 25% | Wednesday 5/7 7:30-9:30pmSame format as the two midterms, but cumulative |
Course Schedule
| Date | Lecture | Readings | Homework |
| Tu 01/14/25 | L01: Course Introduction; ISA and Processor Review | Reading 01: Introduction | HW01: ISA Review and RISC-V Intro assigned |
| Th 01/16/25 | L02: ISA Review and Performance Intro | None; review albaCore as needed or work ahead on next reading | |
| Tu 01/21/25 | L03: Performance | Reading 02: Performance (open until Wed.) | |
| Th 01/23/25 | L04: RISC-V Instructions and Programming | Reading 03: RISC-V Instruction Introduction | HW01 due HW02: Performance and Assembly Programming assigned |
| Tu 01/28/25 | L05: RISC-V Instruction Types and Encodings | Reading 04: RISC-V Instructions (R-, I-, S-, SB-types) | |
| Th 01/30/25 | L06: RISC-V Control and Procedures | Reading 05: RISC-V Procedures (UJ-type, call/return, stack) | HW03: RISC-V ISA and Function Calls assigned HW02 due |
| Tu 02/04/25 | L07: Recursive Function and Pipelining Introduction | Reading 06: Pipelining Intro | |
| Th 02/06/25 | L08: Pipelining | Reading 07: Pipelining Details | HW04 Procedures, Pipelining, and Sorting assigned HW03 due |
| Tu 02/11/25 | L09: Pipelining Hazards | Reading 08: Pipelining Hazards | |
| Th 02/13/25 | L10: Exam 1 Review | No reading due | HW04 due |
| Tu 02/18/25 | Midterm Exam 1 (L11) | No reading due | |
| Th 02/20/25 | L12: Control Hazards | Review Control Hazards from Reading 08 | HW05 Pipeline Control Hazards assigned No HW due |
| Tu 02/25/25 | L13: Control Hazard Examples, Memory Hierarchy Review | Reading 09: Memory Hierarchy Intro/Review of Direct-mapped Caches | |
| Th 02/27/25 | L14: Direct-mapped Caches | Reading 10: AMAT and Set Associative Caches | HW06 Caches assigned HW05 due |
| Tu 03/04/25 | L15: Associative Caches and Cache Examples | No reading due | |
| Th 03/06/25 | L16: Cache Performance (no video) | Reading 11: Improving Cache Performance | HW06 due Friday |
| Tu 03/11/25 | Spring Break | ||
| Th 03/13/25 | Spring Break | ||
| Tu 03/18/25 | L17: Cache-Aware Programming and Virtual Memory Intro | No reading due | |
| Th 03/20/25 | L18: Virtual Memory (Paging) | Reading 13: Virtual Memory | HW07 Cache Performance assigned |
| Tu 03/25/25 | L19: VM Examples and Performance | Reading 14: VM Performance and the TLB | |
| Th 03/27/25 | L20: VM Wrap-up | No reading due | HW07 due HW08 Virtual Memory assigned |
| Tu 04/01/25 | L21: Out-of-order Introduction | Reading 15: Multiple Issue, Static Scheduling | |
| Th 04/03/25 | L22: Midterm Exam 2 Review | No reading due | HW08 due |
| Tu 04/08/25 | Midterm Exam 2 (L23) | No reading due | |
| Th 04/10/25 | L24: Dynamic Scheduling | Reading 16: Dynamic Scheduling | HW09 Out of Order Execution assigned |
| Tu 04/15/25 | L25: Dynamic Scheduling Examples | No reading due | |
| Th 04/17/25 | L26: Multi-core Introduction | Reading 17: Cache Coherence (last reading) | HW09 due HW10 Cache Coherence assigned |
| Tu 04/22/25 | L27: Cache Coherence | No reading due | |
| Th 04/24/25 | L28: Cache Coherence Examples | No reading due | HW10 due |
| Tu 04/29/25 | L29: Wrap-up and Final Exam Review | No reading due |