The information below is based on the Spring 2025 section of CSE 20221.
Overall Course Goals
By the end of the course, you should:
- Have a good basic understanding of the inner workings of a digital computer, including the main structures and abstractions used in a design, from basic Boolean operations made out of switches, up through a complete microprocessor executing an assembly language program.
- Be able to independently design and debug a moderately complex digital system, demonstrating proficiency of critical implementation techniques applicable to both hardware and software design, including the use of appropriate diagrams and tables to guide implementation and using a hypothesis-based approach to identify bugs.
Specific Learning Objectives
By the end of this course you should be able to:
- Formulate logic expressions using the basic AND, OR, and NOT operations and implement these expressions as switching circuits.
- Use the properties of Boolean algebra, as well as graphical tools to simplify logic expressions
- Design fundamental combinational logic building blocks such as decoders, multiplexors, and adders using basic logic gates
- Implement a latch and a register (flip-flop) using primitive logic gates, and to use registers to implement common sequential building blocks such as register files, counters, and timers
- Develop a finite state machine (FSM) diagram that describes sequential behavior and then implement the FSM using registers and combinational logic
- Design a high-level state machine (HLSM) that describes the algorithmic behavior of a digital system and then implement a digital system based on the HLSM with a datapath and FSM
- Explain the organization of a simple multicycle microprocessor and write assembly language programs for that processor
- Explain the need for, organization of, and data movement within a memory hierarchy including the register file, a first-level direct-mapped data cache, and a main memory.
- Use a digital logic design tool and simulator to design and simulate simple combinational logic circuits, storage elements, hardware components for simple functional units, finite state machines, and simple processor datapaths.
Grading
| Homework | 35% | Weighted equally by score as percentage |
| Readings | 5% | zyBook readings will be due on most class days |
| Midterm Exam 1 | 17.5% | Thursday 2/20 in class, on paper |
| Midterm Exam 2 | 17.5% | Thursday 4/10 in class, on paper |
| Final Exam | 25% | Thursday 5/8 7:30pm-9:30pm Same format as the two midterms but cumulative |
Course Schedule
| Date | Lecture | Readings | Homework |
| Tu 01/14/25 | L01: Course Introduction; Bits and Bytes | Reading 01: Introduction | HW01: Number Representation and C assigned |
| Th 01/16/25 | L02: Number Representation | Reading 02: Numbers and Letters | |
| Tu 01/21/25 | L03: Intro to albaCore and Assembly Language | Reading 03: Intro to albaCore and Assembly Language (due Wed 11:59pm) | HW02: Introduction to albaCore and Assembly Language assigned (Tuesday) HW01 due (Wednesday) |
| Th 01/23/25 | L04: More albaCore and Assembly Language | Reading 04: albaCore Load, Store, Branches, and Jumps (due Thurs 9:30am) | |
| Tu 01/28/25 | L05: albaCore Memory and Control Instructions | No reading due | HW03: More albaCore Programming assigned HW02 due |
| Th 01/30/25 | L06: albaCore Control – Selection, Loops and Procedures | Reading 05: Digital Circuits | |
| Tu 02/04/25 | L07: albaCore Control Wrap-up and Digital Logic Intro | Reading 06: Boolean Algebra | HW04 Digital Circuits and Boolean Algebra assigned HW03 due |
| Th 02/06/25 | L08: Digital Logic, Boolean Algebra, Simplification | Reading 07: Logic Optimization | |
| Tu 02/11/25 | L09: K-maps and Combinational Logic Components | Reading 08: Combinational Logic Components (Part 1) | HW05 Adder/Subtractor assigned HW04 due Wed. |
| Th 02/13/25 | L10: More Comb. Logic Components and Adders | Reading 09: Combinational Logic Components (Part 2) | |
| Tu 02/18/25 | L11: Exam 1 Review (extra review examples recording) | No reading due | No HW assigned HW05 due Wed. |
| Th 02/20/25 | Midterm Exam 1 (L12) | No reading due | |
| Tu 02/25/25 | L13: Sequential Logic Introduction | Reading 10: ND Latches and FFs | HW06 Basic Calculator assigned |
| Th 02/27/25 | L14: Flip Flops and Registers | Reading 11: Latches, Flip Flops, and Registers | |
| Tu 03/04/25 | L15: Register Examples | Reading 12: Load Registers, Counters, Timers | HW06 due |
| Th 03/06/25 | L16: Register Files and Memories | Reading 13: Register Files and Memory | |
| Tu 03/11/25 | Spring Break | ||
| Th 03/13/25 | Spring Break | ||
| Tu 03/18/25 | L17: Finite State Machines | Reading 14: Finite State Machines | HW07 Programmable Calculator assigned |
| Th 03/20/25 | L18: Finite State Machine Design | Reading 15: FSM Design and Analysis | |
| Tu 03/25/25 | L19: FSM Examples and HLSM Intro | Reading 16: HLSMs Part 1 | HW07 due HW08 Finite State Machines assigned |
| Th 03/27/25 | L20: High-level State Machines | Reading 17: HLSMs Part 2 | |
| Tu 04/01/25 | L21: HLSM Examples | No reading due | HW08 due HW09 Design of a Hardware Multiplier assigned |
| Th 04/03/25 | L22: Back to albaCore | Reading 18: albaCore HLSM, etc. | |
| Tu 04/08/25 | L23: Midterm Exam 2 Review | No reading due | HW09 due |
| Th 04/10/25 | Midterm Exam 2 (L24) | No reading due | |
| Tu 04/15/25 | L25: albaCore Wrap-up | No reading due | HW10 Caches assigned |
| Th 04/17/25 | L26: Cache Introduction | Reading 19: Caches (Part 1) | |
| Tu 04/22/25 | L27: Direct-mapped Caches | Reading 20: Caches (Part 2) (last reading) | |
| Th 04/24/25 | L28: Direct-Mapped Cache Wrap-up | No reading due | |
| Tu 04/29/25 | L29: Wrap-up and Final Exam Review | HW10 due |