NanoElectronic Devices and Systems (NEEDS)
College of Engineering
Paper 1: Unraveling Intricate Switching Dynamics of FeFETs with Gate Side Injection Towards Reliable Disturb-Immune 3D NAND Storage (Sizhe Ma)
Poster 1: BTI Reliability Enhancement of Ge-Doped In₂O₃ TFTs via Al₂O₃ Passivation (Xingtian Wang)
Poster 2: Investigation into Temperature Dependent 2T-nC FeRAM Readout Operation (Siyuan Li)
Congratulations! Four papers have been accepted at 2025 IEEE IEDM held at San Francisco!
Paper 1: Towards Scalable 3D Integration of 2T-nC FeRAM with Hundreds of Layer Stacking (Jiahui Duan* & Shan Deng*)
Paper 2: Securing 3D NAND Without Density Loss via In-Situ Encryption Using a Single Transistor XOR Cell (Jiahui Duan)
Paper 3: Atomic Layer Deposited Amorphous Ge-Doped Indium Oxide with Enhanced Mobility–Stability–
Crystallization Resistance Tradeoff (YuShan Lee* & Xingtian Wang* & Jiahui Duan*)
Ppaer 4: Comprehensive Evaluation of Challenges in Realizing Disturb-Free Ferroelectric Vertical NAND
via String-Compatible Independent Pass Gates (Xuezhong Niu)
*: Co-first author at NEEDs group
Congratulations to Yushan Lee and John Howe‘s work which were accepted to 2025 Techcon in Austin, TX. And John has been selected to give Undergraduate Lightning Talks in Graduate Sessions. Looking forward to enjoying both presentaions!
Congrations to our undergraduate John Howe‘s paper, titled “Engineering MSMFM Structure Composed of Compound Bi-Directional Selector and Ferroelectric Capacitor for High Density Capacitor Arrays“, was accepted to 2025 Device Research Conference (DRC)!
Congratulations to Shan Deng, John Howe, and Sizhe Ma! Our paper, “Vertical 2T-nC FeRAM Demonstration: BEOL Read Transistor for 4F2 Memory Strings and Two-Terminal Selector Design for Polarization Disturb Mitigation”, has been accepted for presentation at the 2025 Symposium on VLSI Technology and Circuits (VLSI) in Kyoto, Japan.
Paper 1: Investigating Read-After-Write Delay in Ferroelectric FET with Gate-Side Injection (Sizhe Ma)
Paper 2: Retention Analysis of Ferroelectric FETs with Gate-Side Injection for Vertical NAND Storage (Yixin Qin)
Congratulations! Four papers have been accepted at 2024 IEEE IEDM held at San Francisco!
Paper 1: First Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3D Ferroelectric Capacitor Memory (Shan Deng)
Paper 2: Clarifying the Role of Ferroelectric in Expanding the Memory Window of Ferroelectric FETs with Gate-Side Injection: Isolating Contributions from Polarization and Charge Trapping (Yixin Qin)
Paper 3: Variation Tolerant and Energy-Efficient Charge Domain Compute-in-Memory Array with Binary and Multi-Level Cell Ferroelectric FET (Jiahui Duan)
Ppaer 4: On the Origin of Holes During Polarization Reset in Floating Body Ferroelectric FETs Towards Improving Switching Efficiency
