Zheyu Yan

Email:  zyan2 at nd.edu
Office: 254 Fitzpatrick


Zheyu is currently a Ph.D. student in the Department of Computer Science and Engineering in University of Notre Dame.  He received B.S. from Zhejiang University, Hangzhou, China and joined the Notre Dame family in 2019. He is co-advised by Dr. Yiyu Shi and Dr. X. Sharon Hu.

His general research direction is hardware/software co-design for neuromorphic computing. His current interests are uncertainty modeling of non-volatile emerging device-based neural accelerators and achieving efficient DNN inference via co-design efforts.


Ph.D. Student, Computer Science and Engineering, University of Notre Dame, IN, 2019 – present
B.S., Electronic Science and Technology, Zhejiang University, Hangzhou, 2019

Skills and Awards

Coding:   Verilog, Assembly, C, Python
Toolkits:  PyTorch, Vivado, Altium Designer
Award:    China National Scholarship (top 0.2%), 2016

Leadership and Services

Academic Director/Organizer, Model United Nations Association of Zhejiang University, 2015-2018
Teaching Assistant, Theory of Computing, Fall 2019
Teaching Assistant, Elements of Computing II, Spring 2019


  1. Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo, “When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies” in Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2020
  2.  Zheyu Yan, Da-Cheng Juan, X. Sharon Hu and Yiyu Shi, “Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search,” in Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2021 (Invited Paper)
  3. Lei Yang, Weiwen Jiang, Zheyu Yan, Tushar Krishna, Hyouk Jun Kwon, Meng Li, Yiyu Shi, “Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks,” Design Automation Conference (DAC) 2020
  4. Weiwen Jiang, Qiuwen Lou, Zheyu Yan, Lei Yang, Jingtong Hu, X. Sharon Hu and Yiyu Shi, “Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators,” IEEE Transactions on Computers