As the CMOS transistor feature size is approaching its physical limit, we are witnessing an explosion of research endeavors in beyond-CMOS technologies. My work explores circuit and architecture designs that can best exploit the unique features of beyond-CMOS devices to maximize the gain offered by such devices. My research benefits greatly from close collaborations with device experts. Below are the several representation topics.
Processing in memory (PIM) is an attractive architectural paradigm for overcoming the ever-growing challenge of transferring data between a processing element and memory in applications such as machine learning and data analytics applications. Beyond-CMOS devices, such as ferroelectric FETs (FeFETs), can function both as a switch and a storage element, hence is a natural fit for implementing PIM constructs. My group have introduced various FeFET based content addressable memories (e.g., ternary, approximate, multi-bit), general-purpose compute-in-memory arrays, binary crossbars arrays, etc.
A paper introducing an FeFET based compute-in-memory array, co-authored by my Ph.D. student, Dayane Reis, my colleague Mike Niemier and I, received the Best Paper Award from 2018 International Symposium on Low Power Electronics and Design. Another paper from my group received the Best Paper Award from 2009 International Symposium on NanoScale Architectures. Below are other representative papers.
- A.F. Laguna, H. Gamaarachchi, X. Yin, M. Niemier, S. Parameswaran and X. Hu, “Seed-and-vote based in-memory accelerator for DNA read mapping”, International Conference on Computer Aided Design, 2020. Article No. 56, pp. 1–9.
- B. Wu, C. Wang, Z. Wang, Y. Wang, D. Zhang, D. Liu, Y. Zhang and X. Hu, “Field-free 3T2SOT MRAM for non-volatile cache memories”, IEEE Transactions on Circuits and Systems, 2020, pp. 4660–4669.
- D. Reis, A.F. Laguna, M. Niemier and X. Hu, “A fast and energy efficient Computing-in-Memory architecture for few-shot learning applications”, Design Automation and Test in Europe, 2020, pp. 127–132.
Secure hardware and hardware for security. Some unique characteristics, such as ambipolarity, of beyond-CMOS devices make these devices especially suited for building low-cost, secure hardware circuits. My group have introduced several novel circuits to achieve logic obfuscation and/or prevent side channel attacks. We also proposed accelerators for homomorphic encryption. Below are some representative papers.
- M.M. Sharifi, R. Rajaei, P. Cadareanu, P.-E. Gaillardon, Y. Jin, M. Niemier and X. Hu, “A novel TIGFET-based DFF design for improved resilience to power side-channel attacks”, Design Automation and Test in Europe, 2020, pp. 1253–1258.
- P. Wu, D. Reis, X. Hu and J. Appenzeller, “Two-dimensional transistors with reconfigurable polarities for secure circuits”, Nature Electronics, 4,2021, pp. 45–53.
- D. Reis, J. Takeshita, T. Jung, M. Niemier and X. Hu, “Computing-in-Memory for performance and energy efficient homomorphic encryption,” IEEE Transactions on VLSI Systems, 2020, pp. 2300–2313.
For more detailed description about my research projects in this area, please visit my lab at: TBD.
My earlier research in the general circuit and architecture design is related to VLSI design and design automation. I have studied problems in high-level synthesis, VLSI floorplanning, and design of special VLSI circuitry for computationally intensive systems.